Riviera-Pro™

ADVANCED VERFICATION PLATFORM

Riviera-PRO™ addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices.
  • High-Performance Simulator for Mixed Language Designs
  • IEEE VHDL, SystemVerilog, Verilog-AMS, SystemC/C/C++
  • Verification Libraries: UVM, OS-VVM
  • Visual mapping and Debugging: UVM Toolbox, UVM Graph, Transaction streams, Plot viewer
  • Built-in debugging tools provide code tracing, waveform, dataflow, FSM window, coverage, assertion, and memory visualization capabilities
  • Assertion-Based Verification: SVA, PSL
  • › Windows® 10/8/7/2010/2008/2003 Linux® – 32/64-bit