ALINT™

DESIGN RULE CHECKING

ALINT™ design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage.

Top Features:
  • Fast design analysis of complex ASIC/FPGA/SOC designs
  • Phase-Based Linting (PBL) Methodology
  • IEEE VHDL, Verilog and mixed-language designs
  • STARC VHDL or Verilog rule plug-ins
  • DO-254/ED-80 VHDL or Verilog rule plug-ins
  • RMM rule plug-in (both Verilog and VHDL)
  • Custom rule creation (C++ API)
  • Integrated result analysis and debugging environment