Static Design Verification

ALINT-PRO™ is a design verification solution for RTL code focused on general issues analysis including: RTL and post-synthesis simulation mismatches, design coding for optimal synthesis, avoiding problems on further design stages, and coding for portability and reuse.

Top Features:
  • Clock and Reset Networks Analysis
  • Avoiding post RTL and post Synthesis Simulation Mismatches
  • Extensive CDC checks with ALDEC_CDC rule plug-in
  • Code Portability and Reuse
  • DFT Checks
  • SDC™ Support
  • Design Constraints Extension for IP Description Synchronizer’s Structure Verification