Active-HDL™

FPGA DESIGN CREATION AND SIMULATION

Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments.
  • IEEE VHDL, Verilog, SystemVerilog (Design) and SystemC
  • Team-based design Management
  • Mixed Language Simulation and Debugging
  • Multi-FPGA & EDA Tool Design Flow Manager
  • Graphical Design Entry Quickly deploy designs by using Text, Schematic and State Machine
  • Assertion-Based Verification (SVA, PSL, OVA)
  • Support for MATLAB®/Simulink® interface
  • HTML and PDF Design Documentation
  • Windows® 10/8/7/2010/2008/2003 -32/64-bit